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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

CV32E40X Design-Verification environment

CV32E40X Design-Verification environment

4 stage, in-order, compute RISC-V core based on the CV32E40P

4 stage, in-order, compute RISC-V core based on the CV32E40P

CV32E40S Design-Verification environment

CV32E40S Design-Verification environment

4 stage, in-order, secure RISC-V core based on the CV32E40P

4 stage, in-order, secure RISC-V core based on the CV32E40P

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

Functional verification project for the CORE-V family of RISC-V cores.

Functional verification project for the CORE-V family of RISC-V cores.