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4 stage, in-order, secure RISC-V core based on the CV32E40P

The purpose of the repo is to support CORE-V Wally architectural verification

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

CV32E40X Design-Verification environment

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

4 stage, in-order, compute RISC-V core based on the CV32E40P

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Functional verification project for the CORE-V family of RISC-V cores.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

4 stage, in-order, secure RISC-V core based on the CV32E40P

Advanced Verification Methodologies for RISC-V and related IP

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CV32E40S Design-Verification environment

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores