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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Functional verification project for the CORE-V family of RISC-V cores.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

CV32E40X Design-Verification environment

Functional verification project for the CORE-V family of RISC-V cores.

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

CV32E40S Design-Verification environment

CORE-V MCU UVM Environment and Test Bench

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Small and simple APB interrupt controller

The purpose of the repo is to support CORE-V Wally architectural verification

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.