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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Eclipse/FreeRTOS/core-v-mcu example program

Instruction Set Generator initially contributed by Futurewei

Aidge bundle repository, which includes the main modules of the Aidge framework, plus the documentation and tutorials.

python helpers tutorial

Aidge bundle repository fork, including new python helpers

Julian Skublics etrice fork

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Aidge bundle repository, which includes the main modules of the Aidge framework, plus the documentation and tutorials.

Aidge bundle repository, which includes the main modules of the Aidge framework, plus the documentation and tutorials.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.