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Eclipse Hawk is a heterogeneous model indexing framework: it indexes collections of models transparently and incrementally into a NoSQL database, which can be queried in a more efficient and convenient manner. https://eclipse.org/hawk/

Example SDK applications for DevKit

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

Unofficial development fork of U-Boot

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

3rd party: Fork of http://git.yoctoproject.org/cgit/cgit.cgi/meta-zephyr/

3rd party: Fork of http://git.yoctoproject.org/cgit/cgit.cgi/meta-zephyr/

3rd party: Fork of http://git.yoctoproject.org/cgit/cgit.cgi/meta-zephyr/

Oniro Project

https://git.seco.com/pub/i.mx/yocto/5.x/meta-seco-imx

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Aidge's learning module, written in C++, required for models training directly in Aidge