From 138bfc53f8eedd0dfaabb47dcee3e916d2049754 Mon Sep 17 00:00:00 2001
From: Ettore Chimenti <ettore.chimenti@seco.com>
Date: Sat, 12 Nov 2022 16:00:20 +0100
Subject: [PATCH] meta-zephyr-bsp: Add support for stm32f3-seco-d23
Add machine and BSP definitions for SECO JUNO (SBC-D23) for Zephyr
v3.1.0.
Tested with `MACHINE=stm32f3-seco-d23 bitbake zephyr-philosophers`
Closes https://gitlab.eclipse.org/eclipse/oniro-core/oniro/-/issues/359
Signed-off-by: Ettore Chimenti <ettore.chimenti@seco.com>
---
.../machine/include/stm32f3-cortex-m4.inc | 6 +
.../conf/machine/stm32f3-seco-d23.conf | 6 +
...001-dts-arm-stm32f303-add-uart5-node.patch | 35 +
...s-arm-st-add-STM32F302xC-device-tree.patch | 139 ++++
...f3_seco_d23-Add-SECO-JUNO-SBC-D23-bo.patch | 682 ++++++++++++++++++
.../zephyr-kernel/zephyr-kernel-src-3.1.0.inc | 3 +
6 files changed, 871 insertions(+)
create mode 100644 meta-zephyr-bsp/conf/machine/include/stm32f3-cortex-m4.inc
create mode 100644 meta-zephyr-bsp/conf/machine/stm32f3-seco-d23.conf
create mode 100644 meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0001-dts-arm-stm32f303-add-uart5-node.patch
create mode 100644 meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0002-dts-arm-st-add-STM32F302xC-device-tree.patch
create mode 100644 meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0003-boards-arm-stm32f3_seco_d23-Add-SECO-JUNO-SBC-D23-bo.patch
diff --git a/meta-zephyr-bsp/conf/machine/include/stm32f3-cortex-m4.inc b/meta-zephyr-bsp/conf/machine/include/stm32f3-cortex-m4.inc
new file mode 100644
index 0000000..a406178
--- /dev/null
+++ b/meta-zephyr-bsp/conf/machine/include/stm32f3-cortex-m4.inc
@@ -0,0 +1,6 @@
+#@TYPE: Machine
+#@NAME: stm32f3-cortex-m4
+
+#@DESCRIPTION: Machine configuration for Cortex-M4 core of STMicroelectronics STM32F3 SoC.
+
+require conf/machine/include/arm/armv7m/tune-cortexm4.inc
diff --git a/meta-zephyr-bsp/conf/machine/stm32f3-seco-d23.conf b/meta-zephyr-bsp/conf/machine/stm32f3-seco-d23.conf
new file mode 100644
index 0000000..fa109de
--- /dev/null
+++ b/meta-zephyr-bsp/conf/machine/stm32f3-seco-d23.conf
@@ -0,0 +1,6 @@
+#@TYPE: Machine
+#@NAME: seco-stm32f3-d23
+
+#@DESCRIPTION: Machine configuration for SBC SECO-D23
+
+require conf/machine/include/stm32f3-cortex-m4.inc
diff --git a/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0001-dts-arm-stm32f303-add-uart5-node.patch b/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0001-dts-arm-stm32f303-add-uart5-node.patch
new file mode 100644
index 0000000..e8c3e29
--- /dev/null
+++ b/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0001-dts-arm-stm32f303-add-uart5-node.patch
@@ -0,0 +1,35 @@
+From 2237fb44b1dde8b2402a16ba4b22ad5a1e1a8a48 Mon Sep 17 00:00:00 2001
+From: Ettore Chimenti <ettore.chimenti@seco.com>
+Date: Tue, 13 Sep 2022 18:33:13 +0200
+Subject: [PATCH 1/3] dts: arm: stm32f303: add uart5 node
+
+Add missing UART5 node to STM32F303 chip family DTSI.
+
+Signed-off-by: Ettore Chimenti <ettore.chimenti@seco.com>
+---
+ dts/arm/st/f3/stm32f303.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/dts/arm/st/f3/stm32f303.dtsi b/dts/arm/st/f3/stm32f303.dtsi
+index f5fd90ab02ea..96ac37a0e92f 100644
+--- a/dts/arm/st/f3/stm32f303.dtsi
++++ b/dts/arm/st/f3/stm32f303.dtsi
+@@ -37,6 +37,15 @@
+ label = "SPI_2";
+ };
+
++ uart5: serial@40005000 {
++ compatible = "st,stm32-uart";
++ reg = <0x40005000 0x400>;
++ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
++ interrupts = <53 0>;
++ status = "disabled";
++ label = "UART_5";
++ };
++
+ pinctrl: pin-controller@48000000 {
+
+ gpioe: gpio@48001000 {
+--
+2.17.1
+
diff --git a/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0002-dts-arm-st-add-STM32F302xC-device-tree.patch b/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0002-dts-arm-st-add-STM32F302xC-device-tree.patch
new file mode 100644
index 0000000..9e07ca6
--- /dev/null
+++ b/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0002-dts-arm-st-add-STM32F302xC-device-tree.patch
@@ -0,0 +1,139 @@
+From d2f1015651a4fe1ca6742692f4e491e00964692c Mon Sep 17 00:00:00 2001
+From: Ettore Chimenti <ek5.chimenti@gmail.com>
+Date: Wed, 16 Nov 2022 15:43:31 +0100
+Subject: [PATCH 2/3] dts: arm: st: add STM32F302xC device tree
+
+Add ST Micro STM32F302xC family of microcontrollers.
+
+Signed-off-by: Ettore Chimenti <ek5.chimenti@gmail.com>
+---
+ dts/arm/st/f3/stm32f302.dtsi | 16 ++++++
+ dts/arm/st/f3/stm32f302Xc.dtsi | 51 +++++++++++++++++++
+ .../stm32f3/Kconfig.defconfig.stm32f302xc | 14 +++++
+ soc/arm/st_stm32/stm32f3/Kconfig.soc | 4 ++
+ 4 files changed, 85 insertions(+)
+ create mode 100644 dts/arm/st/f3/stm32f302Xc.dtsi
+ create mode 100644 soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc
+
+diff --git a/dts/arm/st/f3/stm32f302.dtsi b/dts/arm/st/f3/stm32f302.dtsi
+index 9541699676cf..3f737c12d08b 100644
+--- a/dts/arm/st/f3/stm32f302.dtsi
++++ b/dts/arm/st/f3/stm32f302.dtsi
+@@ -79,6 +79,22 @@
+ };
+ };
+
++ timers4: timers@40000800 {
++ compatible = "st,stm32-timers";
++ reg = <0x40000800 0x400>;
++ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
++ interrupts = <30 0>;
++ interrupt-names = "global";
++ st,prescaler = <0>;
++ status = "disabled";
++
++ pwm {
++ compatible = "st,stm32-pwm";
++ status = "disabled";
++ #pwm-cells = <3>;
++ };
++ };
++
+ adc1: adc@50000000 {
+ compatible = "st,stm32-adc";
+ reg = <0x50000000 0x400>;
+diff --git a/dts/arm/st/f3/stm32f302Xc.dtsi b/dts/arm/st/f3/stm32f302Xc.dtsi
+new file mode 100644
+index 000000000000..4c1de5611ee2
+--- /dev/null
++++ b/dts/arm/st/f3/stm32f302Xc.dtsi
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (c) 2022 Seco Spa
++ *
++ * SPDX-License-Identifier: Apache-2.0
++ */
++
++#include <mem.h>
++#include <st/f3/stm32f302.dtsi>
++
++/ {
++ sram0: memory@20000000 {
++ reg = <0x20000000 DT_SIZE_K(40)>;
++ };
++
++ soc {
++ flash-controller@40022000 {
++ flash0: flash@8000000 {
++ reg = <0x08000000 DT_SIZE_K(256)>;
++ };
++ };
++
++ dma2: dma@40020400 {
++ compatible = "st,stm32-dma-v2bis";
++ #dma-cells = <2>;
++ reg = <0x40020400 0x400>;
++ clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
++ interrupts = <56 0 57 0 58 0 59 0 60 0>;
++ status = "disabled";
++ };
++
++ uart5: serial@40005000 {
++ compatible = "st,stm32-uart";
++ reg = <0x40005000 0x400>;
++ clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
++ interrupts = <53 0>;
++ status = "disabled";
++ };
++
++ pinctrl: pin-controller@48000000 {
++ gpioe: gpio@48001000 {
++ compatible = "st,stm32-gpio";
++ gpio-controller;
++ #gpio-cells = <2>;
++ reg = <0x48001000 0x400>;
++ clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
++ };
++ };
++ };
++};
++
++/delete-node/ &i2c3;
+diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc
+new file mode 100644
+index 000000000000..5cf16dec891b
+--- /dev/null
++++ b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc
+@@ -0,0 +1,14 @@
++# ST Microelectronics STM32F302XC MCU
++
++# Copyright (c) 2022, SECO Spa
++# SPDX-License-Identifier: Apache-2.0
++
++if SOC_STM32F302XC
++
++config SOC
++ default "stm32f302xc"
++
++config NUM_IRQS
++ default 82
++
++endif # SOC_STM32F302XC
+diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.soc b/soc/arm/st_stm32/stm32f3/Kconfig.soc
+index 135e79b8a49c..6dde4dfd8cfa 100644
+--- a/soc/arm/st_stm32/stm32f3/Kconfig.soc
++++ b/soc/arm/st_stm32/stm32f3/Kconfig.soc
+@@ -10,6 +10,10 @@ choice
+ config SOC_STM32F302X8
+ bool "STM32F302X8"
+
++config SOC_STM32F302XC
++ bool "STM32F302XC"
++ select CPU_HAS_ARM_MPU
++
+ config SOC_STM32F303X8
+ bool "STM32F303X8"
+
+--
+2.17.1
+
diff --git a/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0003-boards-arm-stm32f3_seco_d23-Add-SECO-JUNO-SBC-D23-bo.patch b/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0003-boards-arm-stm32f3_seco_d23-Add-SECO-JUNO-SBC-D23-bo.patch
new file mode 100644
index 0000000..7d4f0ba
--- /dev/null
+++ b/meta-zephyr-core/recipes-kernel/zephyr-kernel/files/0003-boards-arm-stm32f3_seco_d23-Add-SECO-JUNO-SBC-D23-bo.patch
@@ -0,0 +1,682 @@
+From f4cea0616842882b037f3f851cb6475fc0cc3d18 Mon Sep 17 00:00:00 2001
+From: Ettore Chimenti <ettore.chimenti@seco.com>
+Date: Mon, 5 Sep 2022 17:47:38 +0200
+Subject: [PATCH 3/3] boards: arm: stm32f3_seco_d23: Add SECO JUNO SBC-D23
+ board
+
+Add support for SECO JUNO board embedded microcontroller STM32F302VC,
+designed to extend capabilities of the main processor Rockchip PX30.
+The microcontroller provides several interfaces, such as 2 and 4-Wire
+UARTs, USB, CAN, Modbus, 8-channels Timer, SPI, I2C and GPI/Os.
+The communication between the two processors is realized with an
+internal SPI line.
+
+Signed-off-by: Ettore Chimenti <ettore.chimenti@seco.com>
+---
+ boards/arm/stm32f3_seco_d23/Kconfig.board | 8 +
+ boards/arm/stm32f3_seco_d23/Kconfig.defconfig | 11 +
+ boards/arm/stm32f3_seco_d23/board.cmake | 6 +
+ .../doc/img/stm32f3_seco_d23.jpg | Bin 0 -> 39049 bytes
+ boards/arm/stm32f3_seco_d23/doc/index.rst | 242 ++++++++++++++++++
+ .../arm/stm32f3_seco_d23/stm32f3_seco_d23.dts | 240 +++++++++++++++++
+ .../stm32f3_seco_d23/stm32f3_seco_d23.yaml | 18 ++
+ .../stm32f3_seco_d23_defconfig | 32 +++
+ .../arm/stm32f3_seco_d23/support/openocd.cfg | 22 ++
+ dts/arm/st/f3/stm32f302Xc.dtsi | 1 +
+ 10 files changed, 580 insertions(+)
+ create mode 100644 boards/arm/stm32f3_seco_d23/Kconfig.board
+ create mode 100644 boards/arm/stm32f3_seco_d23/Kconfig.defconfig
+ create mode 100644 boards/arm/stm32f3_seco_d23/board.cmake
+ create mode 100644 boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg
+ create mode 100644 boards/arm/stm32f3_seco_d23/doc/index.rst
+ create mode 100644 boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts
+ create mode 100644 boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml
+ create mode 100644 boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig
+ create mode 100644 boards/arm/stm32f3_seco_d23/support/openocd.cfg
+
+diff --git a/boards/arm/stm32f3_seco_d23/Kconfig.board b/boards/arm/stm32f3_seco_d23/Kconfig.board
+new file mode 100644
+index 000000000000..d745a9ce8d08
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/Kconfig.board
+@@ -0,0 +1,8 @@
++# SECO SBC-D23 board configuration
++
++# Copyright (c) 2022, SECO Spa
++# SPDX-License-Identifier: Apache-2.0
++
++config BOARD_STM32F3_SECO_D23
++ bool "SECO JUNO SBC-D23 (STM32F302VC) Board"
++ depends on SOC_STM32F302XC
+diff --git a/boards/arm/stm32f3_seco_d23/Kconfig.defconfig b/boards/arm/stm32f3_seco_d23/Kconfig.defconfig
+new file mode 100644
+index 000000000000..f83d9615416b
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/Kconfig.defconfig
+@@ -0,0 +1,11 @@
++# SECO SBC-D23 board configuration
++
++# Copyright (c) 2022, SECO Spa
++# SPDX-License-Identifier: Apache-2.0
++
++if BOARD_STM32F3_SECO_D23
++
++config BOARD
++ default "stm32f3_seco_d23"
++
++endif # BOARD_STM32F3_SECO_D23
+diff --git a/boards/arm/stm32f3_seco_d23/board.cmake b/boards/arm/stm32f3_seco_d23/board.cmake
+new file mode 100644
+index 000000000000..7959a6039492
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/board.cmake
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: Apache-2.0
++
++board_runner_args(jlink "--device=STM32F302VC" "--speed=4000")
++
++include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
++include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+diff --git a/boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg b/boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg
+new file mode 100644
+index 000000000000..84954dfdeb2e
+Binary files /dev/null and b/boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg differ
+diff --git a/boards/arm/stm32f3_seco_d23/doc/index.rst b/boards/arm/stm32f3_seco_d23/doc/index.rst
+new file mode 100644
+index 000000000000..c551b2f3ca42
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/doc/index.rst
+@@ -0,0 +1,242 @@
++.. _stm32f3_seco_d23_board:
++
++SECO JUNO SBC-D23 (STM32F302)
++#############################
++
++Overview
++********
++
++JUNO (SBC-D23) is a Single Board Computer based on embedded Rockchip PX30
++Processor, featuring Quad-Core ARM Cortex-A35 processor. The processor
++integrates a Mali-G31 GPU with High performance dedicated 2D processor,
++supporting OpenGL ES 1.1 / 2.0 / 3.2, Vulkan 1.0, OpenCL 2.0 and Open VG 1.1.
++Embedded VPU is able to support video decoding of the most common coding
++standard (MPEG-4, H.265/HEVC, H.264, VP8, VC-1). The board is completed with up
++to 4GB LPDDR4-3200 32-bit bus memory directly soldered on board and one eMMC
++5.1 Flash Drive with up to 64GB of capacity. LVDS Single Channel interface and
++HDMI are supported. The RMII interface and Micrel KSZ8091 Ethernet Transceiver
++allow the implementation of a Fast Ethernet interface. The networking
++capabilities can be extended by WiFi+BT M.2 module and external modem module.
++The audio functionalities are managed by the AudioCodec embedded in the RK-809
++PMIC. The JUNO board is completed by a series of connectors with various
++interfaces (UART, SPI, I2C) managed by the microcontroller STM32F302VCT6.
++
++.. image:: img/stm32f3_seco_d23.jpg
++ :align: center
++ :alt: SECO JUNO
++
++More information about the board can be found at the
++`SECO JUNO SBC-D23 website`_.
++
++Hardware
++********
++
++SECO JUNO SBC-D23 provides the following hardware components:
++
++- STM32F302VCT6
++ - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
++ - 256 KB Flash
++ - 40 KB SRAM
++ - 72 MHz max CPU frequency
++- 2 User LEDs
++- 16 GPI
++- 16 GPO
++- 4 U(S)ART
++ - Modbus
++ - RS485
++ - TTL Serial Debug
++ - TTL Serial
++- 8-channel General Purpose Timers
++- USB 2.0 full speed interface
++- CAN
++- I2C (up to 2)
++- SPI
++
++More information about STM32F302VC can be found here:
++
++- `STM32F302VC on www.st.com`_
++- `STM32F302xC reference manual`_
++
++Supported Features
++==================
++
++The Zephyr stm32f3_seco_d23 board configuration supports the following hardware
++features:
++
+++-----------+------------+-------------------------------------+
++| Interface | Controller | Driver/Component |
+++===========+============+=====================================+
++| NVIC | on-chip | nested vector interrupt controller |
+++-----------+------------+-------------------------------------+
++| UART | on-chip | serial port-polling; |
++| | | serial port-interrupt |
+++-----------+------------+-------------------------------------+
++| PINMUX | on-chip | pinmux |
+++-----------+------------+-------------------------------------+
++| GPIO | on-chip | gpio |
+++-----------+------------+-------------------------------------+
++| I2C | on-chip | i2c |
+++-----------+------------+-------------------------------------+
++| SPI | on-chip | spi |
+++-----------+------------+-------------------------------------+
++| USB | on-chip | USB device |
+++-----------+------------+-------------------------------------+
++| CAN | on-chip | CAN |
+++-----------+------------+-------------------------------------+
++| IWDG | on-chip | Independent WatchDoG |
+++-----------+------------+-------------------------------------+
++| PWM | on-chip | pwm |
+++-----------+------------+-------------------------------------+
++
++Other hardware features are not yet supported on Zephyr porting.
++
++Pin Mapping
++===========
++
++SECO-D23 has 6 GPIO controllers. These controllers are
++responsible for pin muxing, input/output, pull-up, etc.
++
++For mode details please refer to `SECO JUNO SBC-D23 board User Manual`_.
++
++Default Zephyr Peripheral Mapping:
++----------------------------------
++
++.. rst-class:: rst-columns
++
++- UART_1_TX : PA9 (debug config for UART_1)
++- UART_1_RX : PA10 (debug config for UART_1)
++- UART_1_TX : PC4 (alternate config for UART_1)
++- UART_1_RX : PC5 (alternate config for UART_1)
++- UART_2_TX : PD5
++- UART_2_RX : PD6
++- UART_2_CLK : PD7
++- UART_2_CTS : PD3
++- UART_2_RTS/DE : PD4
++- UART_3_TX : PC10
++- UART_3_RX : PC11
++- UART_3_CLK : PD10
++- UART_3_CTS : PD11
++- UART_3_RTS/DE : PD12
++- UART_5_TX : PC12
++- UART_5_RX : PD2
++- I2C1_SCL : PB6
++- I2C1_SDA : PB7
++- I2C2_SCL : PA9 (alternate config for UART_1)
++- I2C2_SDA : PA10 (alternate config for UART_1)
++- SPI1_NSS : PA4
++- SPI1_SCK : PB3
++- SPI1_MISO : PB4
++- SPI1_MOSI : PB5
++- SPI2_NSS : PB12
++- SPI2_SCK : PB13
++- SPI2_MISO : PB14
++- SPI2_MOSI : PB15
++- CAN1_RX : PB8
++- CAN1_TX : PB9
++- USB_DM : PA11
++- USB_DP : PA12
++- LD1 : PD8
++- LD2 : PD9
++- PWM : PA8
++
++System Clock
++============
++
++SECO SBC-D23 System Clock could be driven by internal or external
++oscillator, as well as main PLL clock. By default System clock is driven
++by PLL clock at 72 MHz, driven by an external oscillator at 8 MHz.
++
++Serial Port
++===========
++
++SECO SBC-D23 has up to 4 U(S)ARTs. The Zephyr console output
++is assigned to UART1. Default settings are 115200 8N1.
++In debug configuration UART1 is connected to the flashing connector CN56.
++
++UART2 provides Modbus interface to connector CN28.
++UART3 provides RS-485 interface to connectors CN57 and CN48.
++In alternative config, USART2 and USART3 are exposed to connector J2.
++
++UART1 (in alternate config) and UART5 are connected to CN32.
++
++I2C
++===
++SECO SBC-D23 has up to 2 I2Cs. Both are present in connector CN33.
++I2C2 is available only on boards where DEBUG serial is not connected.
++
++USB
++===
++SECO SBC-D23 has a USB 2.0 full-speed device interface available through
++its connector CN31.
++
++CAN
++===
++SECO SBC-D23 has an onboard CAN transceiver (TJA1051T), and it is
++connected to both CN29 and CN30. PD0 is connected to EC_CAN_STBY.
++
++SPI
++===
++SECO SBC-D23 has two SPI lines: SPI1 is an internal SPI line connected to the
++main processor (Rockchip PX30) and SPI2 is connected to CN39.
++
++Programming and Debugging
++*************************
++
++Flashing
++========
++
++Applications for the ``stm32f3_seco_d23`` board configuration can be built and
++flashed in the usual way (see :ref:`build_an_application` and
++:ref:`application_run` for more details).
++
++Flashing an application to SECO SBC-D23
++-------------------------------------------
++
++First, connect the SECO SBC-D23 to your host computer using
++CN56 connector to an ST-Link.
++The pinout is (1-8):
++- VDD
++- UART1_TX
++- UART1_RX
++- BOOT_0
++- SWDIO_JTMS
++- SWCLK_JTCK
++- EC_RST#
++- GND
++
++Then build and flash your application.
++
++Here is an example for the :ref:`hello_world` application.
++
++.. zephyr-app-commands::
++ :zephyr-app: samples/hello_world
++ :board: stm32f3_seco_d23
++ :goals: build flash
++
++Run a serial host program to connect with your board.
++
++.. code-block:: console
++
++ $ minicom -D /dev/<tty device>
++
++Replace <tty_device> with the port where the SBC-D23 board can be
++found.
++
++You should see the following message on the console:
++
++.. code-block:: console
++
++ Hello World! stm32f3_seco_d23
++
++
++.. _SECO JUNO SBC-D23 website:
++ https://edge.seco.com/juno.html
++
++.. _SECO JUNO SBC-D23 board User Manual:
++ https://www.seco.com/Manuals/SBC-D23_Manual.pdf
++
++.. _STM32F302VC on www.st.com:
++ http://www.st.com/en/microcontrollers/stm32f302vc.html
++
++.. _STM32F302xC reference manual:
++ https://www.st.com/resource/en/reference_manual/rm0365-stm32f302xbcde-and-stm32f302x68-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts b/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts
+new file mode 100644
+index 000000000000..3f4750a28ce4
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts
+@@ -0,0 +1,240 @@
++/*
++ * Copyright (c) 2022 Seco Spa
++ *
++ * SPDX-License-Identifier: Apache-2.0
++ */
++
++/dts-v1/;
++#include <st/f3/stm32f302Xc.dtsi>
++#include <st/f3/stm32f302v(b-c)tx-pinctrl.dtsi>
++
++/ {
++ model = "SECO JUNO SBC-D23 board (STM32F302VCT6)";
++ compatible = "seco,stm32f3-d23";
++
++ chosen {
++ zephyr,console = &usart1;
++ zephyr,code-partition = &slot0_partition;
++ zephyr,shell-uart = &usart1;
++ zephyr,sram = &sram0;
++ zephyr,flash = &flash0;
++ zephyr,canbus = &can1;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ led_1: led_1 {
++ gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
++ label = "LED-1";
++ };
++ led_2: led_2 {
++ gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
++ label = "LED-2";
++ };
++ };
++
++ out_3p3v_pwr: 3p3v-out-pwr-ctrl {
++ compatible = "regulator-fixed";
++ regulator-name = "3p3v-out-pwr-ctrl";
++ enable-gpios = <&gpioe 7 GPIO_ACTIVE_HIGH>;
++ regulator-always-on;
++ regulator-boot-on;
++ label = "3P3V-OUT-PWR-CTRL";
++ status = "okay";
++ };
++
++ out_gpio_bufa_pwr: out-gpio-bufa-pwr-ctrl {
++ compatible = "regulator-fixed";
++ regulator-name = "out-gpio-bufa-pwr-ctrl";
++ enable-gpios = <&gpiof 2 GPIO_ACTIVE_LOW>;
++ regulator-boot-on;
++ label = "OUT-GPIO-BUFA-PWR-CTRL";
++ status = "okay";
++ };
++
++ out_gpio_bufb_pwr: out-gpio-bufb-pwr-ctrl {
++ compatible = "regulator-fixed";
++ regulator-name = "out-gpio-bufb-pwr-ctrl";
++ enable-gpios = <&gpiof 4 GPIO_ACTIVE_LOW>;
++ regulator-boot-on;
++ label = "OUT-GPIO-BUFB-PWR-CTRL";
++ status = "okay";
++ };
++
++ in_gpio_buf_pwr: in-gpio-buf-pwr-ctrl {
++ compatible = "regulator-fixed";
++ regulator-name = "in-gpio-buf-pwr-ctrl";
++ enable-gpios = <&gpiof 6 GPIO_ACTIVE_LOW>;
++ regulator-boot-on;
++ label = "IN-GPIO-BUF-PWR-CTRL";
++ status = "okay";
++ };
++
++ transceiver0: can-phy0 {
++ compatible = "nxp,tja1040", "can-transceiver-gpio";
++ standby-gpios = <&gpiod 0 GPIO_ACTIVE_HIGH>;
++ max-bitrate = <1000000>;
++ #phy-cells = <0>;
++ };
++
++ aliases {
++ led0 = &led_1;
++ led1 = &led_2;
++ };
++};
++
++&clk_lsi {
++ status = "okay";
++};
++
++&clk_hse {
++ clock-frequency = <DT_FREQ_M(8)>;
++ status = "okay";
++};
++
++&pll {
++ prediv = <1>;
++ mul = <9>;
++ clocks = <&clk_hse>;
++ status = "okay";
++};
++
++&rcc {
++ clocks = <&pll>;
++ clock-frequency = <DT_FREQ_M(72)>;
++ ahb-prescaler = <1>;
++ apb1-prescaler = <2>;
++ apb2-prescaler = <1>;
++ status = "okay";
++};
++
++/* Debug Serial */
++&usart1 {
++ pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
++ pinctrl-names = "default";
++ current-speed = <115200>;
++ status = "okay";
++};
++
++/* Modbus */
++&usart2 {
++ pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6
++ &usart2_cts_pd3 &usart2_rts_pd4>;
++ pinctrl-names = "default";
++ current-speed = <115200>;
++};
++
++/* RS-485 */
++&usart3 {
++ pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11
++ &usart3_rts_pd12>;
++ pinctrl-names = "default";
++ current-speed = <115200>;
++};
++
++&uart5 {
++ pinctrl-0 = <&uart5_tx_pc12 &uart5_rx_pd2>;
++ pinctrl-names = "default";
++ current-speed = <115200>;
++};
++
++&i2c1 {
++ pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
++ pinctrl-names = "default";
++ clock-frequency = <I2C_BITRATE_FAST>;
++ status = "okay";
++};
++
++&i2c2 {
++ /* alternate config usart1 */
++ pinctrl-0 = <&i2c2_scl_pa9 &i2c2_sda_pa10>;
++ pinctrl-names = "default";
++ clock-frequency = <I2C_BITRATE_FAST>;
++};
++
++&spi1 {
++ pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pb3
++ &spi1_miso_pb4 &spi1_mosi_pb5>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&spi2 {
++ pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
++ &spi2_miso_pb14 &spi2_mosi_pb15>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++zephyr_udc0: &usb {
++ pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&can1 {
++ pinctrl-0 = <&can_rx_pb8 &can_tx_pb9>;
++ pinctrl-names = "default";
++ bus-speed = <125000>;
++ phys = <&transceiver0>;
++ status = "okay";
++};
++
++&flash0 {
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ boot_partition: partition@0 {
++ label = "mcuboot";
++ reg = <0x00000000 0x00010000>;
++ read-only;
++ };
++ /*
++ * The flash starting at 0x00010000 and ending at
++ * 0x0001ffff (sectors 16-31) is reserved for use
++ * by the application.
++ */
++ slot0_partition: partition@20000 {
++ label = "image-0";
++ reg = <0x00020000 0x00008000>;
++ };
++ slot1_partition: partition@28000 {
++ label = "image-1";
++ reg = <0x00028000 0x00008000>;
++ };
++ storage_partition: partition@30000 {
++ label = "storage";
++ reg = <0x00030000 0x00002000>;
++ };
++ scratch_partition: partition@32000 {
++ label = "image-scratch";
++ reg = <0x00032000 0x00008000>;
++ };
++ };
++};
++
++&iwdg {
++ status = "okay";
++};
++
++&timers1 {
++ st,prescaler = <10000>;
++ status = "okay";
++ pwm1: pwm {
++ pinctrl-0 = <&tim1_ch1_pe9 &tim1_ch2n_pe10 &tim1_ch2_pe11
++ &tim1_ch3n_pe12 &tim1_ch3_pe13 &tim1_ch4_pe14>;
++ pinctrl-names = "default";
++ status = "okay";
++ };
++};
++
++&timers4 {
++ st,prescaler = <10000>;
++ status = "okay";
++ pwm4: pwm {
++ pinctrl-0 = <&tim4_ch2_pd13 &tim4_ch3_pd14 &tim4_ch4_pd15>;
++ pinctrl-names = "default";
++ status = "okay";
++ };
++};
+diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml b/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml
+new file mode 100644
+index 000000000000..8ca0b3391228
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml
+@@ -0,0 +1,18 @@
++identifier: stm32f3_seco_d23
++name: SECO JUNO SBC-D23 (STM32F302)
++type: mcu
++arch: arm
++toolchain:
++ - zephyr
++ - gnuarmemb
++ - xtools
++ram: 40
++supported:
++ - gpio
++ - i2c
++ - counter
++ - spi
++ - watchdog
++ - nvs
++ - can
++ - pwm
+diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig b/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig
+new file mode 100644
+index 000000000000..c8038a6da729
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig
+@@ -0,0 +1,32 @@
++# SPDX-License-Identifier: Apache-2.0
++# SECO SBC-D23 board defconfig
++#
++# Copyright (c) 2022, SECO Spa
++
++CONFIG_SOC_SERIES_STM32F3X=y
++CONFIG_SOC_STM32F302XC=y
++
++# Enable MPU
++CONFIG_ARM_MPU=y
++
++# Enable HW stack protection
++CONFIG_HW_STACK_PROTECTION=y
++
++# enable uart driver
++CONFIG_SERIAL=y
++
++# enable console
++CONFIG_CONSOLE=y
++CONFIG_UART_CONSOLE=y
++
++# enable GPIO
++CONFIG_GPIO=y
++
++# clock configuration
++CONFIG_CLOCK_CONTROL=y
++
++# enable regulators
++CONFIG_REGULATOR=y
++
++# enable pin controller
++CONFIG_PINCTRL=y
+diff --git a/boards/arm/stm32f3_seco_d23/support/openocd.cfg b/boards/arm/stm32f3_seco_d23/support/openocd.cfg
+new file mode 100644
+index 000000000000..69be74a07663
+--- /dev/null
++++ b/boards/arm/stm32f3_seco_d23/support/openocd.cfg
+@@ -0,0 +1,22 @@
++# SECO JUNO SBC-D23 board with a single STM32F302VCT6 chip
++# Flashing is possible by connecting the board to an ST-Link via SWD
++# https://edge.seco.com/juno.html
++
++source [find interface/stlink.cfg]
++
++transport select hla_swd
++
++source [find target/stm32f3x.cfg]
++
++reset_config srst_only
++
++$_TARGETNAME configure -event gdb-attach {
++ echo "Debugger attaching: halting execution"
++ reset halt
++ gdb_breakpoint_override hard
++}
++
++$_TARGETNAME configure -event gdb-detach {
++ echo "Debugger detaching: resuming execution"
++ resume
++}
+diff --git a/dts/arm/st/f3/stm32f302Xc.dtsi b/dts/arm/st/f3/stm32f302Xc.dtsi
+index 4c1de5611ee2..6040d74cf30c 100644
+--- a/dts/arm/st/f3/stm32f302Xc.dtsi
++++ b/dts/arm/st/f3/stm32f302Xc.dtsi
+@@ -43,6 +43,7 @@
+ #gpio-cells = <2>;
+ reg = <0x48001000 0x400>;
+ clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
++ label = "GPIOE";
+ };
+ };
+ };
+--
+2.17.1
+
diff --git a/meta-zephyr-core/recipes-kernel/zephyr-kernel/zephyr-kernel-src-3.1.0.inc b/meta-zephyr-core/recipes-kernel/zephyr-kernel/zephyr-kernel-src-3.1.0.inc
index ed7f6c1..24dcb07 100644
--- a/meta-zephyr-core/recipes-kernel/zephyr-kernel/zephyr-kernel-src-3.1.0.inc
+++ b/meta-zephyr-core/recipes-kernel/zephyr-kernel/zephyr-kernel-src-3.1.0.inc
@@ -72,5 +72,8 @@ ZEPHYR_BRANCH = "v3.1-branch"
PV = "3.1.0+git${SRCPV}"
SRC_URI += " \
+ file://0001-dts-arm-stm32f303-add-uart5-node.patch \
+ file://0002-dts-arm-st-add-STM32F302xC-device-tree.patch \
+ file://0003-boards-arm-stm32f3_seco_d23-Add-SECO-JUNO-SBC-D23-bo.patch \
${@bb.utils.contains("ONIRO_ENABLE_ACM0", "1", "file://0001-zephyr-3.1.0-console-enable-the-USB-ACM0-console.patch", "", d)} \
"
--
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