Merge requests · Eclipse Projects / Eclipse ESCET (Supervisory Control Engineering Toolkit) / escet · GitLab

#320 Remove unused algebraic variables

!269 · created Feb 23, 2022 by Albert Hofkamp v0.5
CIF TypeEnhancement
- Merged
- 66
- Approved
updated Mar 02, 2022
#263 Updated release notes for v0.5-M1.

!267 · created Feb 21, 2022 by Dennis Hendriks v0.5
RelEng/DevOps TypeEnhancement
- Merged
- 3
- Approved
updated Feb 22, 2022
#314 Add release dates to release notes

!266 · created Feb 20, 2022 by Ferdie Reijnen v0.5
CIF Chi Products RelEng/DevOps ToolDef TypeEnhancement
- Merged
- Approved
updated Feb 20, 2022
#301 Move CIF type checks for events that may lead to false positives to post checker

!264 · created Feb 09, 2022 by Ferdie Reijnen v0.5
CIF TypeEnhancement
- Merged
- 46
- Approved
updated Feb 14, 2022
#308 Add cif2cif event controllability rewriting transformations.

!263 · created Feb 09, 2022 by Albert Hofkamp v0.5
CIF TypeEnhancement
- Merged
- 84
- Approved
updated Feb 24, 2022
#292 Update raildiagram generator documentation and diagrams.

!260 · created Jan 31, 2022 by Albert Hofkamp v0.5
Common TypeEnhancement
- Merged
- 53
- Approved
updated Feb 05, 2022
#298 CIF may produce false positive duplicate event on edge warnings

!259 · created Jan 31, 2022 by Ferdie Reijnen v0.5
CIF TypeEnhancement
- Merged
- 16
- Approved
updated Feb 04, 2022
#293 #110 #109 Fix layout of the railroad diagrams

!258 · created Jan 21, 2022 by Albert Hofkamp v0.5
Common TypeEnhancement
- Merged
- 45
updated Jan 27, 2022
Draft: Resolve "Railroad diagrams should not use `java.awt` drawing functionality for graphics"

!257 · created Jan 21, 2022 by Albert Hofkamp v0.5
Common TypeEnhancement
- Closed
updated Jan 21, 2022
#111 Generate railroad diagrams during build rather than commiting them to git repo.

!256 · created Jan 19, 2022 by Ferdie Reijnen v0.5
Common RelEng/DevOps TypeEnhancement
- Closed
- 46
updated Mar 19, 2022
Draft: #111 Generate railroad diagrams during build rather than committing them to Git repo

!255 · created Jan 18, 2022 by Ferdie Reijnen v0.5
Common RelEng/DevOps TypeEnhancement
- Closed
- 7
updated Jan 19, 2022
#275 Reconsider assigning all open issues to current release and moving them from release to release

!253 · created Jan 07, 2022 by Ferdie Reijnen v0.5
RelEng/DevOps TypeEnhancement
- Merged
- 4
- Approved
updated Jan 09, 2022
#283 Add raildiagram generator image debug output.

!252 · created Jan 07, 2022 by Albert Hofkamp v0.5
Common TypeEnhancement
- Merged
- 29
updated Jan 13, 2022
#142 CIF to PLC should support Siemens S7

!251 · created Jan 06, 2022 by Ferdie Reijnen v0.5
CIF TypeEnhancement
- Merged
- 72
updated Jan 19, 2024
#274 CIF simulator GUI input mode termination by red stop button leaves buttons enabled

!243 · created Dec 30, 2021 by Ferdie Reijnen v0.5
CIF TypeEnhancement
- Merged
- 6
- Approved
updated Jan 05, 2022
#266 Prepare Git repo for v0.5 development

!241 · created Dec 20, 2021 by Dennis Hendriks v0.5
RelEng/DevOps TypeEnhancement
- Merged
- Approved
updated Dec 20, 2021
#160 No longer sort the generated dependencies file.

!240 · created Dec 18, 2021 by Ferdie Reijnen v0.5
RelEng/DevOps TypeEnhancement
- Merged
- Approved
updated Dec 18, 2021
#262 Merge test plugins into their corresponding non-test plugins

!238 · created Dec 16, 2021 by Ferdie Reijnen v0.5
RelEng/DevOps TypeEnhancement
- Merged
- 39
- Approved
updated Jun 12, 2023
#270 Rename product and releng plugins

!235 · created Dec 13, 2021 by Ferdie Reijnen v0.5
RelEng/DevOps TypeEnhancement
- Merged
- 11
- Approved
updated Dec 17, 2021
#107 Data-based synthesis should support state plant invariants

!159 · created Oct 01, 2021 by Ferdie Reijnen v0.5
CIF TypeEnhancement
- Merged
- 111
- Approved
updated Mar 12, 2022

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