From 888268842e1f4d445022da27c83b1e9efbfe188f Mon Sep 17 00:00:00 2001
From: NAUD Maxence <maxence.naud@cea.fr>
Date: Sun, 20 Oct 2024 13:44:27 +0000
Subject: [PATCH] [TMP] change scheduler test for Merge to be possible
---
aidge_backend_cpu/unit_tests/test_scheduler.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/aidge_backend_cpu/unit_tests/test_scheduler.py b/aidge_backend_cpu/unit_tests/test_scheduler.py
index 0aeeb04b..c37fc544 100644
--- a/aidge_backend_cpu/unit_tests/test_scheduler.py
+++ b/aidge_backend_cpu/unit_tests/test_scheduler.py
@@ -17,12 +17,12 @@ class test_scheduler(unittest.TestCase):
input_node = aidge_core.Producer(aidge_core.Tensor(values), "Input")
relu = aidge_core.ReLU()
+ input_node.add_child(relu)
gv = aidge_core.GraphView()
gv.add(relu)
gv.add(input_node)
- input_node.add_child(relu)
gv.set_datatype(aidge_core.dtype.int32)
gv.set_backend("cpu")
--
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